Journal article
IEEE Transactions on Electron Devices, 2024
APA
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Yusuf, M., Singh, S., Dasgupta, A., Sarkar, B., & Roy, S. (2024). A Space Mapping Augmented Compact Model for Uncertainty Quantification of GaN HEMT Devices and Circuits in the Presence of Trap Effects. IEEE Transactions on Electron Devices.
Chicago/Turabian
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Yusuf, Mohd., Smriti Singh, Avirup Dasgupta, Biplab Sarkar, and Sourajeet Roy. “A Space Mapping Augmented Compact Model for Uncertainty Quantification of GaN HEMT Devices and Circuits in the Presence of Trap Effects.” IEEE Transactions on Electron Devices (2024).
MLA
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Yusuf, Mohd., et al. “A Space Mapping Augmented Compact Model for Uncertainty Quantification of GaN HEMT Devices and Circuits in the Presence of Trap Effects.” IEEE Transactions on Electron Devices, 2024.
BibTeX Click to copy
@article{mohd2024a,
title = {A Space Mapping Augmented Compact Model for Uncertainty Quantification of GaN HEMT Devices and Circuits in the Presence of Trap Effects},
year = {2024},
journal = {IEEE Transactions on Electron Devices},
author = {Yusuf, Mohd. and Singh, Smriti and Dasgupta, Avirup and Sarkar, Biplab and Roy, Sourajeet}
}
In this article, an artificial neural network (ANN) augmented compact model is developed for the fast uncertainty quantification (UQ) of GaN high electron mobility transistors (HEMTs). The proposed model consists of a space mapping neural network (SMNN) that maps the uncertain geometrical, physical, material, bias, and trap-related parameters to the input features of a conventional GaN HEMT compact model. Traditionally, compact models demand repetitive feature retuning for any change in the trap energy levels and/or trap densities leading to a high computational time cost. The proposed augmentation maps the one-time calibrated compact model output to the true device responses for any variability in the trap energy levels and/or trap densities. Therefore, the proposed model can capture the impact of a wide distribution of trap-related parameters on GaN HEMT responses more efficiently than the conventional compact models. Numerical examples are provided to perform device- and circuit-level UQ using the proposed framework.