CMAS Lab

Indian Institute of Technology Roorkee

An Efficient Variability-Aware Control Variate-Assisted Neural Network Model for Advanced Nanoscale Transistors


Journal article


Srishti Parandiyal, Anamika Singh, Kumar Sheelvardhan, Surila Guglani, M. Ehteshamuddin, Sourajeet Roy, A. Dasgupta
International Conference on E-Business and E-Government, 2022

Semantic Scholar DOI
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APA   Click to copy
Parandiyal, S., Singh, A., Sheelvardhan, K., Guglani, S., Ehteshamuddin, M., Roy, S., & Dasgupta, A. (2022). An Efficient Variability-Aware Control Variate-Assisted Neural Network Model for Advanced Nanoscale Transistors. International Conference on E-Business and E-Government.


Chicago/Turabian   Click to copy
Parandiyal, Srishti, Anamika Singh, Kumar Sheelvardhan, Surila Guglani, M. Ehteshamuddin, Sourajeet Roy, and A. Dasgupta. “An Efficient Variability-Aware Control Variate-Assisted Neural Network Model for Advanced Nanoscale Transistors.” International Conference on E-Business and E-Government (2022).


MLA   Click to copy
Parandiyal, Srishti, et al. “An Efficient Variability-Aware Control Variate-Assisted Neural Network Model for Advanced Nanoscale Transistors.” International Conference on E-Business and E-Government, 2022.


BibTeX   Click to copy

@article{srishti2022a,
  title = {An Efficient Variability-Aware Control Variate-Assisted Neural Network Model for Advanced Nanoscale Transistors},
  year = {2022},
  journal = {International Conference on E-Business and E-Government},
  author = {Parandiyal, Srishti and Singh, Anamika and Sheelvardhan, Kumar and Guglani, Surila and Ehteshamuddin, M. and Roy, Sourajeet and Dasgupta, A.}
}

Abstract

In this paper, a novel artificial neural network (ANN) has been developed for the efficient variation-aware modeling of current-voltage (I-V) characteristics of general nanoscale devices. The key innovation of this work lies in the development of a new control variate strategy to significantly shrink the number of technology computer-aided design (TCAD) device simulations required to train the ANN model. Consequently, the proposed ANN model can emulate the drain current of the target device as analytic functions of the device geometry, material, and bias voltages at much smaller computational costs than conventional ANN models. A validation example of a 14nm fin field effect transistor (FinFET) is provided in this paper.